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For this month’s issue, our editorial team interviewed some of the top HDI experts in the PCB supply chain. Joining us on the conference call were Steve Bird, PCB/flex technology manager at Finisar, and Tony Torres of APCT. Also on the call were several technologists from MC Assembly: Vince Burns, quality engineer; Steve Jervey, director of Test Engineering; Mike Smyth, SMT engineer; and Paul Petty, product engineer. This wide-ranging conversation covered the latest technology developments, manufacturing challenges, and HDI strategies, from the design, fabrication, and assembly perspectives.
Andy Shaughnessy: Why don’t we start with design? Steve, you’re an HDI technology manager, so you’re driving this whole thing. Why don’t you tell us where you guys are with HDI?
Steve Bird: Sure. I’m wearing two hats. One is technical lead for the EEs and the CAD designers here at Finisar, and the second one is organic substrate roadmapping and development. Maybe 18 months or two years ago, we were working with a fabricator. We started cheating on the FR-4 design rules, and to their credit they built over 1,500 of these over a period of a year or so and finally gave it up and said, “No bid.” So of course, the upper management team came to my group saying, “You’re violating the design rules.” And I said, “Yes, but not without an engineer sitting next to the CAD designer. And yeah, we did, but what we have here really is not a design rule violation, but a technology limitation.”
That spun off an effort to find a substrate that could support the design rules that we’re cheating to. Our PCB technology team was tasked with the effort. We got one new substrate developed and released, but now those new design rules are being violated; we have to continue development. For that previous generation, once we got off FR-4 and onto alternate materials, we were still in the subtractive process. Now we’re looking very heavily at the semi-additive process. Our trace with normal FR-4 is going from 4 mil trace and space down to say, 3.5 mil, roughly, and that’s what earned us the no-bid. Now we’re at two mil trace and three mil space, and that’s still not good enough.
So, we’re continuing to increase the density, and for us, our whole game is no vias, no stubs, and no parasitics. Everything’s predictable: no glass weave, etc. So what we’re looking at is thinner and thinner laminate, and hybrid stack-ups. We can certainly do all our power delivery and control signal distribution on FR-4 layers, but what lies on that surface is important to us. We can do small modules, system-type modules for our ICs and such, our chip-on-board and so on, but really what we need is a full system-level surface layer that can support those types of densities and mount chips.
That’s really what we are working towards right now. We’re now looking at 20−25-micron traces and 25−40-micron gaps, and seeing if we can’t do that. If we can, then we can support all our chip mounting technologies. We can support our system-level traces that get from the origin to the destination and so on. When we do that, then of course these traces get very lossy, and that becomes a huge concern. So our antidote to that is keep them short. Get them shorter. And so that’s kind of our roadmap in a nutshell. We’re starting with surface density, because the propagation is the fastest, keeping it stubless, and then making the net as short as possible. We run everything that’s important differentially for noise immunity. So, you can imagine the types of stackups we’re looking at in terms of hybrid stack-ups and so on.
Shaughnessy: What sort of materials are working out best for you?
Bird: When we first started this effort, my boss asked me, “What would you use? What’s the first step that you would do?” My response was, “Thin, glass-free laminates. Something that’s just as thin as you can make it.” Let me put it this way: There is a slide that shows FR-4 with traces and spaces in the 4 mil range. With the help of HDI, we then took the through-hole off HDI: TODAY, TOMORROW AND THE FUTURE the surface and stacked the blind and buried vias. We call this technology level modified FR- 4. This got us to 3.5 mil trace/space. There is another slide called the constant impedance funnel for differential pairs. You can imagine this funnel that starts out in the FR-4 at 4 mil trace/space and goes all the way down to be something like chip-on-glass or ceramic at 0.6 mil trace/space. One can place a large bracket in the gap with a label saying “This gap is too large. This gap is responsible for chewing up real estate because things are not scalable.” The things that you do on an IC or on glass, you have a lot of overhead in terms of the splay angle, trying to get the signals out (escaped) and getting them routable.
We are trying to solve that. Because once you solve the trace to be similar to the pin or pad pitch, then your channels become much more scalable on the surface. By the way, as we’re going up in frequency, we’re also going up in channel count. We’re getting whacked from both sides. We need to step back and look at what design rules we need. If we’re at 25-micron trace and 40-micron gap, things such as channel count and speed become much more manageable. Now the trace has become much shorter. From a signal integrity standpoint, the first thing to do is get rid of all your parasitics, get rid of all your stubs, trace, tie-bars, etc., as well as your parallelism and propagation delay; get rid of everything that will kill a signal, and then go for improved material. That’s where we’re at right now. We’re searching the world for the best material with the best copper with the best adhesion, which means the best processes in terms of subtractive, additive or semiadditive. Then of course the vias stick out like a sore thumb, and even 25-micron vias stick out like a sore thumb to us. So it’s very important that we go vialess for all our high-speed traces. If we do that, then we can get to where we want in organic material. My whole point is, let’s be organic if we can, and I don’t think we’re done being creative here.
This article originally appeared in the November 2017 issue of The PCB Magazine, click here.