Just Ask Happy: The Exclusive Compilation
We asked for you to send in your questions for Happy Holden, and you took us up on it! We loved them so much, and we know that you did too, so we’ve compiled all 21 questions and answers into one document for easy reference.
Calculating Trace Temps in a Vacuum
Q: For space applications (without air), how should we calculate external layer current-carrying traces against the IPC-2221 (formerly IPC-D-275) charts?
A: I have never studied that, so I turned this question over to an expert, my friend Mike Jouppi, former committee chair of IPC-2152 Standard for Determining Current Carrying Capacity in Printed Board Design. This standard will provide many answers to your questions. Mike wrote Chapters 22 and 23 in the seventh edition of the Printed Circuits Handbook, edited by Clyde F. Coombs and me.
Mike answered: I'm a mechanical engineer who worked as a career thermal analyst. The charts in IPC-2152 in almost all cases will be conservative (both air and vacuum environments). The vacuum is for space environments. The purpose behind these charts is misconstrued by most users. My intention when they were developed was to use these charts as a baseline for developing thermal models that could be used to better understand the actual temperature rise of conductors in actual designs, which I did for my own design purposes. The concept did not catch on.
There is a significant difference between the temperature rise in a conductor, tested per IPC-TM-2.5.4.1a, and most PWB design configurations. The reason is that most designs have copper ground and power planes that conduct energy away from the traces. In addition, most designs in space applications have a significant conduction path from the PWB through-bolted fasteners or wedge locks to a sink.
Since the question does not include IPC-2152, I would recommend researching IPC-2152 and accounting for the power dissipations in the traces in the thermal design. I also recommend accounting for the conductor power dissipation in all designs, especially if the designers are not familiar with sizing parallel conductors. Parallel conductors are easily managed with accounting for conductor losses (power dissipation). FYI: It was the power dissipation in conductors that motivated me to lead the development of IPC-2152.
Ranking the Top Countries by Fab Technology and Production
Q: In terms of overall PCB fabrication capability, how would you rank these countries in terms of technology and production, today and in 10 years: USA, Japan, Korea, Taiwan, China, Thailand, Vietnam, India, Germany, and the U.K.?
A: I don’t have a crystal ball, but here is my best guess:
Manufacturing Issues From a Designer’s Viewpoint
Q: What do you think are the biggest PCB fabrication/assembly issues from a designer’s perspective?
A: Communication and education! Designers need to know a lot about electrical circuits and their performance, but equally important is knowing how that circuit will be manufactured. But manufacturing is usually not part of a designer’s education, so designers have to go out of their way to meet the manufacturing community and to communicate with them on issues related to their designs. IPC and SMTA make this type of training available, but a designer has to be aggressive in learning about manufacturing and all the do’s and don’ts.
Flexible Circuit Technology of the Future
Q: What do you think will be the next leading-edge technology for flexible circuits?
A: Disposable and wearable substrates, including paper
Monitoring Via Reliability on a Lot-by-Lot Basis
Q: What is the best way to monitor microvia reliability on a lot-by-lot basis for high-volume production?
A: What I recommend, and practice, is this: Do a thorough qualification of a fabricator using a HATS Qualification Panel (an IPC PCQRR-like panel) that includes an IPC D coupon resized for the runner on your SMT panel. Run these panel coupons through IPC-TM-650-2.6.27B and then TM-650-2.6.7.2 thermal cycles for 500 cycles. This is your baseline.
Then, by incorporating this smaller D coupon on all your boards’ assembly runners—requiring each lot to have a plating process control coupon for X number of solder float tests at 288°C and then microsections to look at TH quality—you have a way of comparing that lot’s performance to your initial qualification for that vendor. This should be redone each year and kept for records on each lot in case needed later.
The Future of 3D Printing
Q: What is your opinion on the 3D printers that can utilize both conductive and non-conductive inks? Is this the future of PCBs?
A: These 3D printers are evolving rapidly. A must is that the printer has the ability to use a number of different inks for the different components of a PCB, including the curing of the inks. At a minimum, that is:
- Insulating substrate
- Low-ohmic conductive ink
- Non-conductive insulating crossover
As the equipment improves, solder masks, resistive/capacitive and solder paste inks, and even semiconductor inks would be nice. Currently, this is a quick-turn application for a few breadboards.
Whether this technology moves into being a source of operational electronics with sufficient reliability will depend on the innovations in creating future inks. Conventional PCB production continues to innovate to reduce their turnaround times and costs, forcing 3D printing to work that much harder on their solutions.
What Would You Change About the Industry?
Q: If you could change/improve one aspect of this industry, what would it be, and why?
A: TQM/continuous improvement (or Six Sigma) is a philosophy that has stuck with me since I was first exposed to it. I even taught the engineering aspects of TQM to every one of my engineers and techs; this included engineering statistics from the free NIST Engineering Statistics Handbook, as well as enhanced problem solving. Then, I would have my engineers teach TQM to their production supervisors, foremen, and leads, who would—with the help of the engineers and techs—teach it to all of the workers.
Continuous improvement is a strategy for success. And in our challenging industry characterized by innovation and change, continuous improvement and customer satisfaction are the only ways to survive and prosper.
Is PCB Fab Returning to the U.S.?
Q: If the U.S. brings more PCB fabrication back to America, will it more likely be to the captive or contract shops?
A: There are only a few captive fabricators in the U.S., but I hope that more OEMs will consider going captive as a way to ensure a source of supplies, lower costs, minimum lead times, and continuous improvements. OEMs should emulate the activities of Whelen Engineering, the emergency lighting company in New Hampshire that went captive and returned all of its PCB fabrication from China. Whelen cut its costs in half, improved quality, ensured its IP security, and cut weeks off their cycle time—all with an investment that had an ROI of fewer than two years.
But if PCB fabrication is to return to the U.S. from abroad, the majority will be to contract shops. If so, I hope that the OEMs will consider partnering with those contract shops and not treating their manufacturing “as just another commodity,” just as they don’t consider their proprietary circuits to be commodities. How circuits are manufactured is not like making soap; each PCB is different and deserves the necessary focus and care in its construction.
Electroless Copper vs. Direct Metallization
Q: What are your thoughts on electroless copper vs. direct metallization?
A: Both get the job done! Electroless copper is the more traditional method but may have some problems with its internal crystalline strength when used with stacked microvias. Direct metallization is a newer technology that has come a long way in their development and is one of the few ways to successfully metallize polyimide film for flex.
Two-Layer Low-Speed PCBs
Q: Why do many two-layer boards work in low-speed applications, signal integrity-wise?
A: Two-layer boards, properly designed, will even work in high-speed applications! Even a single-sided board will. If the signal rise times are slow, signal integrity does not enter in the solution.
Resin-Filled Vias Without Voids
Q: What is the best way to resin-fill vias without voids?
A: I have not used this process a lot. In the past, partially filling surface vias with solder mask was sufficient. But now, with via-in-pad and stacked microvias, the filling process must be much more complete. Several machines on the market do this job very adequately and can be seen at the IPC APEX EXPO or SMTA International.
Integrating Design Processes With IEEE HIR
Q: How will the PCB design process change to align with the IEEE Heterogeneous Integration Roadmap (HIR), and do you think this will happen?
A: This is happening now! New EDA system tools are being created for the growing automotive complexity of autonomous vehicles. These tools can also be applied to other electronic systems, such as mobile phones, 5G networking, medical, space, high-performance computing, and IoT. In the past, we called these chip-on-board (COB), multi-chip modules (MCM), and system-in-packages (SIP).
The new name is heterogeneous integrated modules (HIM). Heterogeneous was chosen because the future modules will incorporate not just IC chips, but also power devices, passive discretes, photonics, MEMS, sensors, antennas, and batteries. Systems-on-chip (SoC) will continue to be an activity, but as Moore’s Law has flattened out, using multiple-cores processor chips w/memory is more cost-effective for greater computing power. As applications grow—and size, cost, and weight are more critical—HIM offers the best choice to move all of these elements closely together in a module.
A good summary paper on this topic was written by Paul Wesling at the SMTA 2020 Pan-Pacific Conference, “The Heterogeneous Integrated Roadmap: Enabling Technology For Systems of the Future,” available from SMTA in August. For more details, the 584-page HIR is available at pwesling.com/hir. Its 23 chapters cover the full gamut of topics related to integrated modules, from today to 2033, for all major electronics markets.
Mechanically Drilled Blind and Buried Vias
Q: Why are mechanical blind and buried vias popular in certain market sectors, yet they never took off in others?
A: Blind and buried vias have their advantages. If only a few are needed, then they can be mechanically drilled. But in markets where miniaturization is essential, and the volumes are high, the laser is the drilling machine of choice.
PCB Design For EE Undergrads?
Q: Do you think that PCB design should be added to an undergraduate EE curriculum?
A: I think it should be an elective that engineering students could take. It is an essential part of the electronics development process, and a PCB design course will work well with a signal and power integrity elective.
Stacked Microvia Reliability Issues
Q: Stacked microvias look good on paper, but they may have reliability problems. What are the best rules for designing stacked microvias to ensure a reliable PCB?
A: The current best practice is stacking no more than two layers, and then moving over for the next buried or blind via or stacking two layers there. The stacked vias should never be stacked on any buried vias.
An IPC committee is currently testing various stacked via configurations to have a comparison for reliability and testing coupons and design. Hopefully, they will also get at the root cause of why stacked microvias are failing at their interface.
Flexible Circuits and 5G
Q: Will flexible circuits be considered an integral interconnect for 5G technology?
A: Yes. Flex circuits will evolve to fulfill the needs of 5G. What may change are the “connections” as millimeter-wave devices, and IIoT can be used to connect signals in 3D and at angles instead of using flex.
Ground Reference Planes
Q: How important are GND reference planes in signals that are less than 50MHz, since 1/4 wavelength is about 30 inches?
A: GND is an essential part of the circuit. The return path for DC is the lowest resistance, but for the AC part of the signal, it is the lowest inductance.
The Future of Mechanical Blind, Buried Vias
Q: Do mechanical blind and buried vias have a future?
A: Yes, especially for the newly invented VeCS technology, which uses a mechanical drill to gain the same density as laser-drilled microvias, but with higher reliability. For more information, read this series on VeCS technology by Joan Tourné of NextGin Technology, which ran in PCB007 Magazine in 2019 (also read Part 2, Part 3, and Part 4).
Routing BGAs With High-Speed Differential Pairs
Q: What advice can you give for routing BGAs with high-speed diff pairs when the routing of these signals so often cuts off routing channels for other signals?
A: This can be a complex topic, as there are a lot of circumstances that require consideration. My advice is to download a great book written by Charles Pfeil when he was an engineering director at Mentor. “BGA Breakouts and Routing: Effective Design Methods for Very Large BGAs” can be downloaded from Mentor’s library, and print copies are available for purchase from Amazon. Charles covers all of the options and boundary conditions that can come up, and he discusses the topic in the details that it requires.
The Proper Order of Design Techniques to Improve Connectivity
Q: There are usually several ways to improve connectivity on any board (including HDI boards). But are there any general principles for which order these features should be added to achieve the best results?
A: From a connectivity and density improvement standpoint, the use of blind vias (either drilled or lasered) offers the greatest gain, especially since the pitch of active components that drives density is shrinking. Next is the reduction of the diameter of via holes and smaller annual rings. Reducing traces and spaces comes next if you do not run into impedance and signal losses, and then blind vias. The final step is adding more layers.
Flexible Circuit Reliability Concerns
Q: What are the key reliability concerns for flexible circuits moving to newer technologies, materials, and processes?
A: The reliability concerns for flex are the same as for rigid circuits, with the exception of flexing. Material performance, conductor performance, external factors, usage, cleanliness, assembly, etc., are all important. Raza Ghaffarian of the Jet Propulsion Laboratory wrote a great review of flex reliability in the 7th edition of “The Printed Circuit Handbook,” which I co-edited with Clyde F. Coombs.
